PTP support with FPGA. Fullstack (hardware/software) development | CEE-SECR 2016 PTP support with FPGA. Fullstack (hardware/software) development – CEE-SECR 2016
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Presentations

PTP support with FPGA. Fullstack (hardware/software) development

Presentation will cover problem categories that are not suitable for solving on general-purpose processors. And which fit well on FPGA architecture.

As example we will observe PTP support on System-On-Chip FPGA.

In our example FPGA firmware will contain network packets timestamping and PTP Hardware Clock modules.

Denis Gabidullin

Denis Gabidullin

Lead developer, STC Metrotek

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Gold

Deutsche Bank Technology CentreJetBrainsSAPFirst Line Software

Silver

Dell Technologies

Embedded

Auriga

Sponsors

T-SystemsKaspersky Lab

Main partners

RUSSOFTAP KITSECON

In cooperation

Association for Computing MachineryACM Special Interest Group on Software Engineering

Technical partners

Hosting-CenterVirtuozzoSoftInvent7pap StudioPrint SalonGroup MPrezent.ru

With support of

RAEC

Organizers

Software Russiai-Help

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